Network devices, such as routers and switches, often utilize modules and cards to implement interfaces and ports to provide interconnectivity to other network devices and allow the network device to be configured to meet the particular requirements of a particular network node.
The network devices must provide a switching fabric to allow the transfer of data and other information between modules and cards. A common implementation of a switching fabric is a bus system, such as the PCI bus, where PCI bus defines an interface between a host CPU and a number of peripheral devices. The number of peripheral devices connected can be increased by utilizing PCI to PCI (P2P) bridges to couple PCI bus segments and extend the bus.
A single memory map applies to all the PCI bus segments so that a given memory address specifies a unique PCI bus segment and device on the segment. The PCI allows for bus masters so that, for examples, two network devices may communicate directly without CPU intervention. However, since the PCI bus system is hierarchical in the sense that communication between devices is managed by the P2P bridges and devices on different segments must be managed by multiple P2P bridges, there can be high latency when bus segments or busy and arbitration is complicated.
The CPU is the root device in the PCI hierarchy which is useful in network devices that use a centralized processing model where functions such as security processing is performed by the CPU for all network modules.
However, many network devices utilize a distributed processing model where processing is performed on the network modules without the use of the CPU to avoid latency due to the need to access the CPU and memory through multiple P2P bridges and bus segments.
The challenges in the field of switching fabrics continue to increase with demands for more and better techniques having greater flexibility and speed. Therefore, a need has arisen for a new system and method for coupling modules in a network device.